The present invention relates to a digital information data recording and reproducing apparatus which is suitable for recording a digital image signal on a recording medium such as a disk, etc. and for reproducing it.
Heretofore, a digital information data recording apparatus for recording a digital information data such as a digital video signal, etc. on a recording medium such as a disk, etc. has been known. In general, since the digital video signal, etc. has much information, a highly efficient coding is adopted in order to compress a transmitted data amount. In various highly efficient codings, a practical use of a DCT (Discrete Cosine Transform) is advanced.
A digital information data recording apparatus shown in FIG. 1 is previously proposed as the digital information data recording device using the DCT. As shown FIG. 1, an input terminal 1 is supplied with a video data which a digitized video data. The video data supplied to the input terminal 1 is supplied to a blocking circuit 2.
In the blocking circuit 2, the video data in an order of an interlace scan is converted into a data having a structure of, for example, a DCT block (8.times.8). That is, two blocks (4.times.8) at the same spatial position in time-continuous first and second fields are combined to each other, so that the block (8.times.8) is formed. In the block (8.times.8), a pixel data on an odd-numbered line is included in the first field, and a pixel data on an even-numbered line is included in the second field.
An output from the blocking circuit 2 is supplied to a shuffling circuit 3. An error is concentrated by a drop out, etc., whereby a deterioration of an image quality is generated. In order to prevent the deterioration of the image quality, in the shuffling circuit 3, such a process that a plurality of macro blocks MB are defined as a unit in one frame and the spatial position is varied from an original position, that is, a shuffling is carried out. In this example, a shuffling unit is equal to a buffering unit BU, and the unit is defined as five micro blocks (5 MB).
The output from the shuffling circuit 3 is supplied to a DCT (cosine conversion) circuit 4 and a movement detecting circuit 5. A coefficient data of (8.times.8) (that is, the coefficient data of a direct current component DC and an alternating current component AC) is generated from the DCT circuit 4. Relating to a moving block, the DCT circuit 4 is switched in such a manner that the DCT in the field is carried out relative to the block (4.times.8) included in the block (8.times.8).
The macro block MB is a plurality of blocks in which the coefficient data of the block (8.times.8) per DCT block is collected. For example, in case of the video data of a component method (Y:CB:CR=4:1:1) of a 525/60 system, as shown in FIGS. 2A and 3, four Y blocks Y.sub.1, Y.sub.2, Y.sub.3, Y.sub.4, one CB block and one CR block at the same position in one frame, that is, the total six blocks constitute one macro block MB.
In case of a sampling frequency of fsc (fsc: color subcarrier frequency), the image in one frame is (910 samples.times.525 lines), and an effective data in the image is defined as (720 samples.times.480 lines). In the component method, the number of all the blocks in one frame is obtained by the following equation : (720.times.6/4).times.480.div.(8.times.8)=8100. Accordingly, 8100.div.6=1350 is the number of the macro blocks MB in one frame.
The DC (direct current component) coefficient data in the coefficient data of (8.times.8) generated in the DCT circuit 4 is not compressed, and it is transmitted to the following-stage circuit. Remaining sixty-three AC coefficient data are supplied to a quantization circuit 7 via a buffer 6. As shown in FIG. 4, the AC coefficient data is sequentially transmitted from a low-order alternating current component to a high-order one in a zigzag-scan order. Furthermore, the AC coefficient data is also supplied to a classifying circuit 8 and a data amount estimate circuit 9.
The buffer 6 delays the coefficient data for a time necessary to determine an appropriate quantization number QNo by the estimate circuit 9. The buffer 6 is also to output each coefficient data of a still block and the moving block in a predetermined order. The quantization number QNo from the estimate circuit 9 is supplied to the quantization circuit 7, and also transmitted to the following stage.
The coefficient data from the DCT circuit 4 is generated in case of the DCT conversion in the frame. If the movement is detected by the movement detecting circuit 5, the DCT process in the field is selected. Specifically, it is an in-field DCT that the DCT is carried out for each of two blocks (4.times.8) at the same position in the time-continuous first and second fields.
If the block moves between the fields, the movement detecting circuit 5 detects the movement, and an in-frame DCT is changed into the in-field DCT in response to the detection. Based on a vertical coefficient data of when an Hadamard conversion is carried out relative to the image data in the block (8.times.8), a judgment of stillness/movement is carried out for every block. In addition, based on an absolute value of a difference between the fields, the movement may be detected.
In case of the in-field DCT, the coefficient data of the block (4.times.8) relating to the first field and the coefficient data of the block (4.times.8) relating to the second field are generated. As shown in FIG. 5, the coefficient data are processed as an arrangement of (8.times.8) located at upper and lower portions. A direct current component DC1 is included in the coefficient data in the first field. Similarly, a direct current component DC2 is also included in the second field. If the coefficient data in each field is independently processed, the following processes of the in-frame DCT and the in-field DCT must be processed independently of each other. As a result, there is such a problem that a scale of a hardware is increased, etc. Accordingly, instead of the direct current component DC2 in the second field, a differential direct current component .DELTA. DC2=(=DC1-DC2) is transmitted.
A detection signal (movement flag) M from the movement detecting circuit 5 is supplied to the data amount estimate circuit 9. The movement flag M is inserted into the recording data in the following stage. In the data amount estimate circuit 9, the movement flag M is used in order to switch the order of outputting the coefficient data and the method of dividing an area according to the stillness/movement.
The quantization circuit 7 quantizes the alternating current component in the coefficient data. That is, in an appropriate quantization step, the AC coefficient data is divided, and its quotient is made as an integer. The quantization step is determined by the quantization number QNo from a QNo controller 10. In case of the digital information data recording apparatus, the process such as an edition, etc. is carried out by one field unit or one frame unit. Accordingly, it is necessary that a generated data amount per one field or one frame is a target value or less.
The data amount generated by the DCT and a variable length coding is changed according to a pattern to be coded. Accordingly, in order that the generated data amount by a buffering unit shorter than one field or one frame period may be the target value or less, a buffering process is carried out. The buffering unit is shortened in order that a buffering circuit may be simplified, for example, a memory capacity for buffering may be reduced, etc. In this example, five macro blocks (5 MB) (=30 DCT blocks) are defined as a buffering unit BU.
Furthermore, the classifying circuit 8 examines a fineness of the pattern at the macro block MB unit. An activity of the macro block MB is classified into four-step classes. An 2-bit activity code AT indicative of the class is generated by the classifying circuit 10. The detected result is supplied to the QNo controller 10. Furthermore, the activity code AT is inserted into the recording data in the following stage.
The output from the quantization circuit 7 is supplied to a variable length coding circuit 11, and a run length coding, a Huffman coding and the like are carried out therein. For example, a run length being a continuous number of "0" of the coefficient data and the coefficient data value are provided for a Huffman table stored in an ROM. A two-dimensional Huffman coding which generates a variable length code (coded output) is adopted. A coded signal from the variable length coding circuit 11 is supplied to the following stage.
Relating to the estimate circuit 9, a Huffman table 12 same as that referred to the variable length coding circuit 11 is provided. The Huffman table 12 generates a bit number data of an output data when the variable length coding is carried out. The estimate circuit 9 judges an optimum set of quantization step. The judged output therefrom is supplied to the QNo controller 10. The QNo controller 10 controls the quantization circuit 7 such that it may quantize the coefficient data by using the set of quantization step. Furthermore, the quantization number QNo for identifying the set of quantization step is transmitted from the QNo controller 10 to the following stage.
In the following-stage fixed length framing circuit 13, the data generated by the above process (the DC coefficient DCT, the variable length coded output, the quantization number QNo, the movement flag M, the activity code AT) are converted into a framing structure for an error correction coding process and the recording data. The recording data having a sync block SB structure is obtained from the framing circuit 13. The recording data is recorded on a hard disk.
By the way, in the framing circuit 13, the compressed data shown in FIG. 2A of 5 macro blocks (1 buffer unit) is packed in 5 sync blocks (5 SB) of 25 Mbps shown in FIGS. 2B, 2C, 2D to thereby carry out a framing process for forming the recording data.
Specifically, in FIGS. 2A to 2E, a shading portion denotes an effective data portion, and a blank portion denotes an ineffective data portion. In the framing circuit 13, in the first place, a pass 1 process is carried out such that the macro blocks MB.sub.1 to MB.sub.5 themselves of the compressed data shown in FIG. 2A may be packed in the macro blocks MB.sub.1 to MB.sub.5 in corresponding containers whose capacity is 25 Mbps shown in FIG. 2B, respectively.
In this case, when an extra data a is generated, a pass 2 process is carried out so that the extra data a may be packed in the blank portion in the same macro block from the beginning as shown in FIG. 2C.
When an extra data b which cannot be put into the same macro block by the pass 2 process is generated, a pass 3 process is carried out. In the pass 3 process, the extra data b is sequentially packed from the beginning of the blank portion of all the macro blocks MB.sub.1 to MB.sub.5 shown in FIG. 2D of one buffering unit BU.
In this case, after the framing process, a data format is shown in FIG. 2E. As shown in FIG. 2E, one sync block SB comprises 2 data in a sync data portion and 38 data in an information data portion, that is, 40 data. One data comprises 16 bits. In respective macro blocks MB, for example, as shown in FIG. 2E, the pass 1, pass 2 and pass 3 processes are carried out. Whenever the effective data is over, an end of block EOB is inserted.
In FIG. 2E, a reference symbol QNo denotes the quantization number. A reference symbol STA denotes an error information. A reference symbol AT denotes a classification information. A reference symbol M denotes the movement flag. A reference symbol DC denotes a direct current component information.
When such a framed recording data is recorded in the recording medium such as a hard disk, etc., the capacity of the recording medium such as the hard disk, etc. can be saved.
However, in even such a framed recording data, the ineffective data portion shown in FIGS. 2E and 3A (the blank portion in FIG. 2E and "0" portion in FIG. 6A) exists over a relatively wide portion.